Benchmark ADC16 Datenblatt Seite 95
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1.).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1.).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
Bit 7:6= SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bit 5:3 = SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0]
SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
70
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
70
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
PR Prescaling factor SCP1 SCP0
100
301
410
13 1 1
TR dividing factor SCT2 SCT1 SCT0
1000
2001
4010
8011
16 1 0 0
32 1 0 1
64 1 1 0
128 1 1 1
RR dividing factor SCR2 SCR1 SCR0
1000
2001
4010
8011
16 1 0 0
32 1 0 1
64 1 1 0
128 1 1 1
- ST72334J/N 1
- ST72314J/N, ST72124J 1
- Table of Contents 2
- 2 INTRODUCTION 6
- 3 PIN DESCRIPTION 7
- (N versions) 8
- (J versions) 9
- 4 REGISTER & MEMORY MAP 13
- 5 FLASH PROGRAM MEMORY 17
- 6 DATA EEPROM 18
- Interrupt enable 21
- Latch Access Transfer 21
- 8 CENTRAL PROCESSING UNIT 23
- Half carry 24
- Interrupt mask 24
- Negative 24
- Carry/borrow 24
- 00000001 25
- MAIN CLOCK 26
- CONTROLLER 26
- ■ an external source 30
- ■ an external RC oscillator 30
- LVD reset flag 32
- Clock security syst 32
- interrupt enable 32
- Watchdog reset flag 32
- 10 INTERRUPTS 33
- INTERRUPTS (Cont’d) 34
- Table 5. Interrupt mapping 34
- 11 POWER SAVING MODES 35
- 12 I/O PORTS 39
- Hardware Configuration 41
- OPEN-DRAIN OUTPUT 41
- PUSH-PULL OUTPUT 41
- Data register 8 bits 44
- Option register 8 bits 44
- I/O PORTS (Cont’d) 45
- 13 MISCELLANEOUS REGISTERS 46
- Main clock out selection 47
- CPU clock prescaler 47
- Slow mode select 47
- Must always be cleared 48
- Beep control 48
- SS mode selection 48
- SS internal mode 48
- 14 ON-CHIP PERIPHERALS 49
- Activation bit 50
- 7-bit timer (MSB to LSB) 50
- Watchdog flag 50
- WATCHDOG TIMER (Cont’d) 51
- Time base control 53
- Oscillator interrupt enable 53
- Oscillator interrupt flag 53
- clock speed) with the choice 54
- 16-BIT TIMER (Cont’d) 55
- Beginning of the sequence 56
- Sequence completed 56
- /CC[1:0]) 58
- 16-BIT FREE RUNNING 59
- OLVL2OLVL1 64
- Pulse Width Modulation cycle 65
- Input Capture Flag 1 69
- Output Compare Flag 1 69
- Timer Overflow Flag 69
- Input Capture Flag 2 69
- Output Compare Flag 2 69
- CAPTURE STROBE 77
- VR02131B 77
- Write Collision status 83
- Mode Fault flag 83
- TDRE TC RDRF IDLE OR NF FE 93
- R8 T8 - M WAKE - 94
- TIE TCIE RIE ILIE TE RE RWU 94
- First SCI Prescaler 95
- SCI Transmitter rate divisor 95
- SCI Receiver rate divisor 95
- 8-bit Extended Receive Pres 96
- 8-bit Extended Transmit Pres 96
- CH2 CH1CH3COCO 0 ADON 0 CH0 97
- ■ A/D conversion [duration: t 98
- D7 D6 D5 D4 D3 D2 D1 D0 99
- COCO 0 ADON 0 CH3 CH2 CH1 CH0 99
- 15 INSTRUCTION SET 101
- Relative (Indirect) 103
- INSTRUCTION GROUPS (Cont’d) 105
- 16 ELECTRICAL CHARACTERISTICS 107
- 16.6 MEMORY CHARACTERISTICS 122
- 16.6.2 EEPROM Data Memory 122
- 16.6.3 FLASH Program Memory 122
- R=10k~10MΩ 124
- UNUSED I/O PORT 128
- ADC Accuracy 139
- 17 PACKAGE CHARACTERISTICS 140
- ■ Heraeus: PD945, PD955 143
- ■ Loctite: 3615, 3298 143
- MICROCONTROLLER OPTION LIST 146
- DEVELOPMENT TOOLS (Cont’d) 148
- 18.4 ST7 APPLICATION NOTES 149
- 19 IMPORTANT NOTES 151
- 20 SUMMARY OF CHANGES 152
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