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RESET SEQUENCE MANAGER (Cont’d)
9.2.2 Asynchronous External RESET
pin
The RESET
pin is both an input and an open-drain
output with integrated R
ON
weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 16).
Starting from the external RESET pulse recogni-
tion, the device RESET
pin acts as an output that
is pulled low during at least t
w(RSTL)out
.
9.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET
pin acts as an output that is
pulled low when V
DD
<V
IT+
(rising edge) or
V
DD
<V
IT-
(falling edge) as shown in Figure 16.
The LVD filters spikes on V
DD
larger than t
g(VDD)
to
avoid parasitic resets.
9.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET
pin acts as an output that is pulled
low during at least t
w(RSTL)out
.
Figure 16. RESET Sequences
V
DD
RUN
RESET PIN
EXTERNAL
WATCHDOG
DELAY
V
IT+
V
IT-
t
h(RSTL)in
t
w(RSTL)out
RUN
DELAY
t
h(RSTL)in
DELAY
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUN RUN
DELAY
RUN
RESET
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (4096 T
CPU
)
FETCH VECTOR
- ST72334J/N 1
- ST72314J/N, ST72124J 1
- Table of Contents 2
- 2 INTRODUCTION 6
- 3 PIN DESCRIPTION 7
- (N versions) 8
- (J versions) 9
- 4 REGISTER & MEMORY MAP 13
- 5 FLASH PROGRAM MEMORY 17
- 6 DATA EEPROM 18
- Interrupt enable 21
- Latch Access Transfer 21
- 8 CENTRAL PROCESSING UNIT 23
- Half carry 24
- Interrupt mask 24
- Negative 24
- Carry/borrow 24
- 00000001 25
- MAIN CLOCK 26
- CONTROLLER 26
- ■ an external source 30
- ■ an external RC oscillator 30
- LVD reset flag 32
- Clock security syst 32
- interrupt enable 32
- Watchdog reset flag 32
- 10 INTERRUPTS 33
- INTERRUPTS (Cont’d) 34
- Table 5. Interrupt mapping 34
- 11 POWER SAVING MODES 35
- 12 I/O PORTS 39
- Hardware Configuration 41
- OPEN-DRAIN OUTPUT 41
- PUSH-PULL OUTPUT 41
- Data register 8 bits 44
- Option register 8 bits 44
- I/O PORTS (Cont’d) 45
- 13 MISCELLANEOUS REGISTERS 46
- Main clock out selection 47
- CPU clock prescaler 47
- Slow mode select 47
- Must always be cleared 48
- Beep control 48
- SS mode selection 48
- SS internal mode 48
- 14 ON-CHIP PERIPHERALS 49
- Activation bit 50
- 7-bit timer (MSB to LSB) 50
- Watchdog flag 50
- WATCHDOG TIMER (Cont’d) 51
- Time base control 53
- Oscillator interrupt enable 53
- Oscillator interrupt flag 53
- clock speed) with the choice 54
- 16-BIT TIMER (Cont’d) 55
- Beginning of the sequence 56
- Sequence completed 56
- /CC[1:0]) 58
- 16-BIT FREE RUNNING 59
- OLVL2OLVL1 64
- Pulse Width Modulation cycle 65
- Input Capture Flag 1 69
- Output Compare Flag 1 69
- Timer Overflow Flag 69
- Input Capture Flag 2 69
- Output Compare Flag 2 69
- CAPTURE STROBE 77
- VR02131B 77
- Write Collision status 83
- Mode Fault flag 83
- TDRE TC RDRF IDLE OR NF FE 93
- R8 T8 - M WAKE - 94
- TIE TCIE RIE ILIE TE RE RWU 94
- First SCI Prescaler 95
- SCI Transmitter rate divisor 95
- SCI Receiver rate divisor 95
- 8-bit Extended Receive Pres 96
- 8-bit Extended Transmit Pres 96
- CH2 CH1CH3COCO 0 ADON 0 CH0 97
- ■ A/D conversion [duration: t 98
- D7 D6 D5 D4 D3 D2 D1 D0 99
- COCO 0 ADON 0 CH3 CH2 CH1 CH0 99
- 15 INSTRUCTION SET 101
- Relative (Indirect) 103
- INSTRUCTION GROUPS (Cont’d) 105
- 16 ELECTRICAL CHARACTERISTICS 107
- 16.6 MEMORY CHARACTERISTICS 122
- 16.6.2 EEPROM Data Memory 122
- 16.6.3 FLASH Program Memory 122
- R=10k~10MΩ 124
- UNUSED I/O PORT 128
- ADC Accuracy 139
- 17 PACKAGE CHARACTERISTICS 140
- ■ Heraeus: PD945, PD955 143
- ■ Loctite: 3615, 3298 143
- MICROCONTROLLER OPTION LIST 146
- DEVELOPMENT TOOLS (Cont’d) 148
- 18.4 ST7 APPLICATION NOTES 149
- 19 IMPORTANT NOTES 151
- 20 SUMMARY OF CHANGES 152
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