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16.11 COMMUNICATION INTERFACE CHARACTERISTICS
16.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
DD
,
f
OSC
, and T
A
unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS
, SCK, MOSI, MISO).
Figure 95. SPI Slave Timing Diagram with CPHA=0
3)
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master
f
CPU
=8MHz
f
CPU
/128
0.0625
f
CPU
/4
2
MHz
Slave
f
CPU
=8MHz
0
f
CPU
/2
4
t
r(SCK)
t
f(SCK)
SPI clock rise and fall time see I/O port pin description
t
su(SS)
SS setup time Slave 120
ns
t
h(SS)
SS hold time Slave 120
t
w(SCKH)
t
w(SCKL)
SCK high and low time
Master
Slave
100
90
t
su(MI)
t
su(SI)
Data input setup time
Master
Slave
100
100
t
h(MI)
t
h(SI)
Data input hold time
Master
Slave
100
100
t
a(SO)
Data output access time Slave 0 120
t
dis(SO)
Data output disable time Slave 240
t
v(SO)
Data output valid time
Slave (after enable edge)
120
t
h(SO)
Data output hold time 0
t
v(MO)
Data output valid time
Master (before capture edge)
0.25
t
CPU
t
h(MO)
Data output hold time 0.25
SS
INPUT
SCK
INPUT
CPHA=0
MOSI
INPUT
MISO
OUTPUT
CPHA=0
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
v(SO)
t
a(SO)
t
su(SI)
t
h(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
seenote2
CPOL=0
CPOL=1
t
su(SS)
t
h(SS)
t
dis(SO)
t
h(SO)
see
note 2
BIT1 IN
- ST72334J/N 1
- ST72314J/N, ST72124J 1
- Table of Contents 2
- 2 INTRODUCTION 6
- 3 PIN DESCRIPTION 7
- (N versions) 8
- (J versions) 9
- 4 REGISTER & MEMORY MAP 13
- 5 FLASH PROGRAM MEMORY 17
- 6 DATA EEPROM 18
- Interrupt enable 21
- Latch Access Transfer 21
- 8 CENTRAL PROCESSING UNIT 23
- Half carry 24
- Interrupt mask 24
- Negative 24
- Carry/borrow 24
- 00000001 25
- MAIN CLOCK 26
- CONTROLLER 26
- ■ an external source 30
- ■ an external RC oscillator 30
- LVD reset flag 32
- Clock security syst 32
- interrupt enable 32
- Watchdog reset flag 32
- 10 INTERRUPTS 33
- INTERRUPTS (Cont’d) 34
- Table 5. Interrupt mapping 34
- 11 POWER SAVING MODES 35
- 12 I/O PORTS 39
- Hardware Configuration 41
- OPEN-DRAIN OUTPUT 41
- PUSH-PULL OUTPUT 41
- Data register 8 bits 44
- Option register 8 bits 44
- I/O PORTS (Cont’d) 45
- 13 MISCELLANEOUS REGISTERS 46
- Main clock out selection 47
- CPU clock prescaler 47
- Slow mode select 47
- Must always be cleared 48
- Beep control 48
- SS mode selection 48
- SS internal mode 48
- 14 ON-CHIP PERIPHERALS 49
- Activation bit 50
- 7-bit timer (MSB to LSB) 50
- Watchdog flag 50
- WATCHDOG TIMER (Cont’d) 51
- Time base control 53
- Oscillator interrupt enable 53
- Oscillator interrupt flag 53
- clock speed) with the choice 54
- 16-BIT TIMER (Cont’d) 55
- Beginning of the sequence 56
- Sequence completed 56
- /CC[1:0]) 58
- 16-BIT FREE RUNNING 59
- OLVL2OLVL1 64
- Pulse Width Modulation cycle 65
- Input Capture Flag 1 69
- Output Compare Flag 1 69
- Timer Overflow Flag 69
- Input Capture Flag 2 69
- Output Compare Flag 2 69
- CAPTURE STROBE 77
- VR02131B 77
- Write Collision status 83
- Mode Fault flag 83
- TDRE TC RDRF IDLE OR NF FE 93
- R8 T8 - M WAKE - 94
- TIE TCIE RIE ILIE TE RE RWU 94
- First SCI Prescaler 95
- SCI Transmitter rate divisor 95
- SCI Receiver rate divisor 95
- 8-bit Extended Receive Pres 96
- 8-bit Extended Transmit Pres 96
- CH2 CH1CH3COCO 0 ADON 0 CH0 97
- ■ A/D conversion [duration: t 98
- D7 D6 D5 D4 D3 D2 D1 D0 99
- COCO 0 ADON 0 CH3 CH2 CH1 CH0 99
- 15 INSTRUCTION SET 101
- Relative (Indirect) 103
- INSTRUCTION GROUPS (Cont’d) 105
- 16 ELECTRICAL CHARACTERISTICS 107
- 16.6 MEMORY CHARACTERISTICS 122
- 16.6.2 EEPROM Data Memory 122
- 16.6.3 FLASH Program Memory 122
- R=10k~10MΩ 124
- UNUSED I/O PORT 128
- ADC Accuracy 139
- 17 PACKAGE CHARACTERISTICS 140
- ■ Heraeus: PD945, PD955 143
- ■ Loctite: 3615, 3298 143
- MICROCONTROLLER OPTION LIST 146
- DEVELOPMENT TOOLS (Cont’d) 148
- 18.4 ST7 APPLICATION NOTES 149
- 19 IMPORTANT NOTES 151
- 20 SUMMARY OF CHANGES 152
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