Benchmark ADC16 Datenblatt Seite 34

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ST72334J/N, ST72314J/N, ST72124J
34/153
INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
Table 5. Interrupt mapping
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from
ACTIVE-HALT mode only.
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
1)
Address
Vector
RESET Reset
N/A
Highest
Priority
Lowest
Priority
yes FFFEh-FFFFh
TRAP Software Interrupt no FFFCh-FFFDh
0 Not used FFFAh-FFFBh
1
MCC/RTC
CSS
Main Clock Controller Time Base Interrupt
or Clock Security System Interrupt
MCCSR
CRSR
yes
FFF8h-FFF9h
2 ei0 External Interrupt Port A3..0
N/A
FFF6h-FFF7h
3 ei1 External Interrupt Port F2..0 FFF4h-FFF5h
4 ei2 External Interrupt Port B3..0 FFF2h-FFF3h
5 ei3 External Interrupt Port B7..4 FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SPI SPI Peripheral Interrupts SPISR
no
FFECh-FFEDh
8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh
9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE9h
10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE7h
11 Data-EEPROM Data EEPROM Interrupt EECSR FFE4h-FFE5h
12
Not used
FFE2h-FFE3h
13 FFE0h-FFE1h
I BIT SET?
Y
N
IRET?
Y
N
FROM RESET
LOAD PC FROM INTERRUPT VECTOR
STACK PC, X, A, CC
SET I BIT
FETCH NEXT INSTRUCTION
EXECUTE INSTRUCTION
THIS CLEARS I BIT BY DEFAULT
RESTORE PC, X, A, CC FROM STACK
INTERRUPT
Y
N
PENDING?
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