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16-BIT TIMER (Cont’d)
14.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The Pulse Width Modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functions cannot be used
when the PWM mode is activated.
Procedure
To use Pulse Width Modulation mode:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if OLVL1=0
and OLVL2=1, using the formula in the oppo-
site column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits).
If OLVL1=1 and OLVL2=0, the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OC
i
R register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
t = Signal or pulse period (in seconds)
f
CPU
= CPU clock frequency (in hertz)
PRESC
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 14 Clock
Control Bits)
If the timer clock is an external clock the formula is:
Where:
t = Signal or pulse period (in seconds)
f
EXT
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 41)
Notes:
1. After a write instruction to the OC
i
HR register,
the output compare function is inhibited until the
OC
i
LR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected from the timer. The ICAP2 pin can be
used to perform input capture (ICF2 can be set
and IC2R can be loaded) but the user must
take care that the counter is reset after each
period and ICF1 can also generate an interrupt
if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
Counter
OCMP1 = OLVL2
Counter
= OC2R
OCMP1 = OLVL1
When
When
= OC1R
Pulse Width Modulation cycle
Counter is reset
to FFFCh
ICF1 bit is set
OC
i
R Value =
t
*
f
CPU
PRESC
- 5
OC
i
R = t
*
f
EXT
-5
- ST72334J/N 1
- ST72314J/N, ST72124J 1
- Table of Contents 2
- 2 INTRODUCTION 6
- 3 PIN DESCRIPTION 7
- (N versions) 8
- (J versions) 9
- 4 REGISTER & MEMORY MAP 13
- 5 FLASH PROGRAM MEMORY 17
- 6 DATA EEPROM 18
- Interrupt enable 21
- Latch Access Transfer 21
- 8 CENTRAL PROCESSING UNIT 23
- Half carry 24
- Interrupt mask 24
- Negative 24
- Carry/borrow 24
- 00000001 25
- MAIN CLOCK 26
- CONTROLLER 26
- ■ an external source 30
- ■ an external RC oscillator 30
- LVD reset flag 32
- Clock security syst 32
- interrupt enable 32
- Watchdog reset flag 32
- 10 INTERRUPTS 33
- INTERRUPTS (Cont’d) 34
- Table 5. Interrupt mapping 34
- 11 POWER SAVING MODES 35
- 12 I/O PORTS 39
- Hardware Configuration 41
- OPEN-DRAIN OUTPUT 41
- PUSH-PULL OUTPUT 41
- Data register 8 bits 44
- Option register 8 bits 44
- I/O PORTS (Cont’d) 45
- 13 MISCELLANEOUS REGISTERS 46
- Main clock out selection 47
- CPU clock prescaler 47
- Slow mode select 47
- Must always be cleared 48
- Beep control 48
- SS mode selection 48
- SS internal mode 48
- 14 ON-CHIP PERIPHERALS 49
- Activation bit 50
- 7-bit timer (MSB to LSB) 50
- Watchdog flag 50
- WATCHDOG TIMER (Cont’d) 51
- Time base control 53
- Oscillator interrupt enable 53
- Oscillator interrupt flag 53
- clock speed) with the choice 54
- 16-BIT TIMER (Cont’d) 55
- Beginning of the sequence 56
- Sequence completed 56
- /CC[1:0]) 58
- 16-BIT FREE RUNNING 59
- OLVL2OLVL1 64
- Pulse Width Modulation cycle 65
- Input Capture Flag 1 69
- Output Compare Flag 1 69
- Timer Overflow Flag 69
- Input Capture Flag 2 69
- Output Compare Flag 2 69
- CAPTURE STROBE 77
- VR02131B 77
- Write Collision status 83
- Mode Fault flag 83
- TDRE TC RDRF IDLE OR NF FE 93
- R8 T8 - M WAKE - 94
- TIE TCIE RIE ILIE TE RE RWU 94
- First SCI Prescaler 95
- SCI Transmitter rate divisor 95
- SCI Receiver rate divisor 95
- 8-bit Extended Receive Pres 96
- 8-bit Extended Transmit Pres 96
- CH2 CH1CH3COCO 0 ADON 0 CH0 97
- ■ A/D conversion [duration: t 98
- D7 D6 D5 D4 D3 D2 D1 D0 99
- COCO 0 ADON 0 CH3 CH2 CH1 CH0 99
- 15 INSTRUCTION SET 101
- Relative (Indirect) 103
- INSTRUCTION GROUPS (Cont’d) 105
- 16 ELECTRICAL CHARACTERISTICS 107
- 16.6 MEMORY CHARACTERISTICS 122
- 16.6.2 EEPROM Data Memory 122
- 16.6.3 FLASH Program Memory 122
- R=10k~10MΩ 124
- UNUSED I/O PORT 128
- ADC Accuracy 139
- 17 PACKAGE CHARACTERISTICS 140
- ■ Heraeus: PD945, PD955 143
- ■ Loctite: 3615, 3298 143
- MICROCONTROLLER OPTION LIST 146
- DEVELOPMENT TOOLS (Cont’d) 148
- 18.4 ST7 APPLICATION NOTES 149
- 19 IMPORTANT NOTES 151
- 20 SUMMARY OF CHANGES 152
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