Benchmark ADC16 Datenblatt

Rev. 2.5April 2003 1/153ST72334J/N,ST72314J/N, ST72124J8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES Memories– 8

ST72334J/N, ST72314J/N, ST72124J10/153PIN DESCRIPTION (Cont’d)For external pin connection guidelines, refer to Section 16 "ELECTRICAL CHARACTERIS

ST72334J/N, ST72314J/N, ST72124J100/1538-BIT A/D CONVERTER (ADC) (Cont’d)Table 19. ADC Register Map and Reset Values Address(Hex.)Register Label765432

ST72334J/N, ST72314J/N, ST72124J101/15315 INSTRUCTION SET 15.1 ST7 ADDRESSING MODESThe ST7 Core features 17 different addressingmodes which can be cla

ST72334J/N, ST72314J/N, ST72124J102/153ST7 ADDRESSING MODES (Cont’d)15.1.1 InherentAll Inherent instructions consist of a single byte.The opcode fully

ST72334J/N, ST72314J/N, ST72124J103/153ST7 ADDRESSING MODES (Cont’d)15.1.6 Indirect Indexed (Short, Long)This is a combination of indirect and short i

ST72334J/N, ST72314J/N, ST72124J104/15315.2 INSTRUCTION GROUPSThe ST7 family devices use an Instruction Setconsisting of 63 instructions. The instruct

ST72334J/N, ST72314J/N, ST72124J105/153INSTRUCTION GROUPS (Cont’d)Mnemo Description Function/Example Dst Src H I N Z CADC Add with Carry A = A + M + C

ST72334J/N, ST72314J/N, ST72124J106/153INSTRUCTION GROUPS (Cont’d)Mnemo Description Function/Example Dst Src H I N Z CJRULE Jump if (C + Z = 1) Unsign

ST72334J/N, ST72314J/N, ST72124J107/15316 ELECTRICAL CHARACTERISTICS16.1 PARAMETER CONDITIONSUnless otherwise specified, all voltages are re-ferred to

ST72334J/N, ST72314J/N, ST72124J108/15316.2 ABSOLUTE MAXIMUM RATINGSStresses above those listed as “absolute maxi-mum ratings” may cause permanent dam

ST72334J/N, ST72314J/N, ST72124J109/153ABSOLUTE MAXIMUM RATINGS (Cont’d)16.2.3 Thermal Characteristics Symbol Ratings Value UnitTSTGStorage temperat

ST72334J/N, ST72314J/N, ST72124J11/15324 VSS_3S Digital Ground Voltage25 15 15 10 PF0/MCO I/O CTX ei1 X X Port F0 Main clock output (fOSC/2)26 16 16 1

ST72334J/N, ST72314J/N, ST72124J110/15316.3 OPERATING CONDITIONS16.3.1 General Operating Conditions Figure 55. fOSC Maximum Operating Frequency Versus

ST72334J/N, ST72314J/N, ST72124J111/153OPERATING CONDITIONS (Cont’d)16.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general ope

ST72334J/N, ST72314J/N, ST72124J112/153FUNCTIONAL OPERATING CONDITIONS (Cont’d)Figure 60. High LVD Threshold Versus VDD and fOSC for ROM devices 2)Fig

ST72334J/N, ST72314J/N, ST72124J113/15316.4 SUPPLY CURRENT CHARACTERISTICSThe following current consumption specified forthe ST7 functional operating

ST72334J/N, ST72314J/N, ST72124J114/153SUPPLY CURRENT CHARACTERISTICS (Cont’d)16.4.2 WAIT and SLOW WAIT Modes Figure 65. Typical IDD in WAIT vs. fCPUF

ST72334J/N, ST72314J/N, ST72124J115/153SUPPLY CURRENT CHARACTERISTICS (Cont’d)16.4.3 HALT and ACTIVE-HALT Modes 16.4.4 Supply and Clock ManagersThe pr

ST72334J/N, ST72314J/N, ST72124J116/15316.5 CLOCK AND TIMING CHARACTERISTICSSubject to general operating conditions for VDD, fOSC, and TA.16.5.1 Gener

ST72334J/N, ST72314J/N, ST72124J117/153CLOCK AND TIMING CHARACTERISTICS (Cont’d)16.5.3 Crystal and Ceramic Resonator OscillatorsThe ST7 internal clock

ST72334J/N, ST72314J/N, ST72124J118/153CLOCK AND TIMING CHARACTERISTICS (Cont’d)16.5.3.2 Typical Ceramic ResonatorsNote:tSU(OSC) is the typical oscill

ST72334J/N, ST72314J/N, ST72124J119/153CLOCK AND TIMING CHARACTERISTICS (Cont’d)Table 22. Typical Ceramic Resonators Table 23. Resonator Frequency Cor

ST72334J/N, ST72314J/N, ST72124J12/153Notes:1. In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull

ST72334J/N, ST72314J/N, ST72124J120/153CLOCK CHARACTERISTICS (Cont’d)16.5.4 RC OscillatorsThe ST7 internal clock can be supplied with an RCoscillator.

ST72334J/N, ST72314J/N, ST72124J121/153CLOCK CHARACTERISTICS (Cont’d)16.5.5 Clock Security System (CSS) Figure 73. Typical Safe Oscillator Frequencie

ST72334J/N, ST72314J/N, ST72124J122/15316.6 MEMORY CHARACTERISTICS16.6.1 RAM and Hardware Registers 16.6.2 EEPROM Data Memory 16.6.3 FLASH Program M

ST72334J/N, ST72314J/N, ST72124J123/15316.7 EMC CHARACTERISTICSSusceptibility tests are performed on a sample ba-sis during product characterization.1

ST72334J/N, ST72314J/N, ST72124J124/153EMC CHARACTERISTICS (Cont’d)16.7.2 Absolute Electrical SensitivityBased on three different tests (ESD, LU and D

ST72334J/N, ST72314J/N, ST72124J125/153EMC CHARACTERISTICS (Cont’d)16.7.2.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required

ST72334J/N, ST72314J/N, ST72124J126/153EMC CHARACTERISTICS (Cont’d)16.7.3 ESD Pin Protection StrategyTo protect an integrated circuit against Electro-

ST72334J/N, ST72314J/N, ST72124J127/153EMC CHARACTERISTICS (Cont’d)True Open Drain Pin ProtectionThe centralized protection (4) is not involved in the

ST72334J/N, ST72314J/N, ST72124J128/15316.8 I/O PORT PIN CHARACTERISTICS16.8.1 General CharacteristicsSubject to general operating conditions for VDD,

ST72334J/N, ST72314J/N, ST72124J129/153I/O PORT PIN CHARACTERISTICS (Cont’d)16.8.2 Output Driving Current Subject to general operating conditions for

ST72334J/N, ST72314J/N, ST72124J13/1534 REGISTER & MEMORY MAPAs shown in the Figure 5, the MCU is capable ofaddressing 64K bytes of memories and I

ST72334J/N, ST72314J/N, ST72124J130/153I/O PORT PIN CHARACTERISTICS (Cont’d)Figure 87. Typical VOL vs. VDD (standard I/Os)Figure 88. Typical VOL vs. V

ST72334J/N, ST72314J/N, ST72124J131/15316.9 CONTROL PIN CHARACTERISTICS16.9.1 Asynchronous RESET PinSubject to general operating conditions for VDD, f

ST72334J/N, ST72314J/N, ST72124J132/153CONTROL PIN CHARACTERISTICS (Cont’d)Figure 91. Typical ION vs. VDD with VIN=VSSFigure 92. Typical VOL at VDD=5V

ST72334J/N, ST72314J/N, ST72124J133/153CONTROL PIN CHARACTERISTICS (Cont’d)16.9.2 ISPSEL PinSubject to general operating conditions for VDD, fOSC, and

ST72334J/N, ST72314J/N, ST72124J134/15316.10 TIMER PERIPHERAL CHARACTERISTICSSubject to general operating conditions for VDD,fOSC, and TA unless other

ST72334J/N, ST72314J/N, ST72124J135/15316.11 COMMUNICATION INTERFACE CHARACTERISTICS16.11.1 SPI - Serial Peripheral InterfaceSubject to general operat

ST72334J/N, ST72314J/N, ST72124J136/153COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)Figure 96. SPI Slave Timing Diagram with CPHA=11)Figure 97. SPI

ST72334J/N, ST72314J/N, ST72124J137/153COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)16.11.2 SCI - Serial Communications InterfaceSubject to genera

ST72334J/N, ST72314J/N, ST72124J138/15316.12 8-BIT ADC CHARACTERISTICSSubject to general operating conditions for VDD, fOSC, and TA unless otherwise s

ST72334J/N, ST72314J/N, ST72124J139/1538-BIT ADC CHARACTERISTICS (Cont’d)ADC Accuracy Figure 99. ADC Accuracy CharacteristicsNotes:1. ADC Accuracy vs.

ST72334J/N, ST72314J/N, ST72124J14/153REGISTER & MEMORY MAP (Cont’d)Table 2. Hardware Register Map Address BlockRegister LabelRegister NameReset S

ST72334J/N, ST72314J/N, ST72124J140/15317 PACKAGE CHARACTERISTICS17.1 PACKAGE MECHANICAL DATA Figure 100. 64-Pin Thin Quad Flat PackageFigure 101. 56-

ST72334J/N, ST72314J/N, ST72124J141/153PACKAGE MECHANICAL DATA (Cont’d)Figure 102. 44-Pin Thin Quad Flat PackageFigure 103. 42-Pin Plastic Dual In-Lin

ST72334J/N, ST72314J/N, ST72124J142/153and PPORT is the port power dissipation determined by the user.2. The average chip-junction temperature can be

ST72334J/N, ST72314J/N, ST72124J143/15317.2 SOLDERING AND GLUEABILITY INFORMATIONRecommended soldering information given onlyas design guidelines in F

ST72334J/N, ST72314J/N, ST72124J144/15318 DEVICE CONFIGURATION AND ORDERING INFORMATIONEach device is available for production in user pro-grammable v

ST72334J/N, ST72314J/N, ST72124J145/153DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)18.2 TRANSFER OF CUSTOMER CODECustomer code is made up of

ST72334J/N, ST72314J/N, ST72124J146/153MICROCONTROLLER OPTION LISTCustomer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST72334J/N, ST72314J/N, ST72124J147/15318.3 DEVELOPMENT TOOLSSTMicroelectronics offers a range of hardwareand software development tools for the ST7 m

ST72334J/N, ST72314J/N, ST72124J148/153DEVELOPMENT TOOLS (Cont’d)18.3.1 Suggested List Of Socket TypesTable 28. Suggested List of TQFP64 Socket Types

ST72334J/N, ST72314J/N, ST72124J149/15318.4 ST7 APPLICATION NOTES IDENTIFICATION DESCRIPTIONEXAMPLE DRIVERSAN 969 SCI COMMUNICATION BETWEEN ST7 AND PC

ST72334J/N, ST72314J/N, ST72124J15/153002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W002Bh CRSR Clock, Reset, Supply Control / Status Register

ST72334J/N, ST72314J/N, ST72124J150/153AN 982 USING ST7 WITH CERAMIC RESONATORAN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTIONAN1015 SOFTWARE TECHNIQU

ST72334J/N, ST72314J/N, ST72124J151/15319 IMPORTANT NOTES19.1 SCI Baud rate registersCaution: The SCI baud rate register (SCIBRR)MUST NOT be written t

ST72334J/N, ST72314J/N, ST72124J152/15320 SUMMARY OF CHANGESDescription of the changes between the current release of the specification and the previo

ST72334J/N, ST72314J/N, ST72124J153/153Notes:Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no res

ST72334J/N, ST72314J/N, ST72124J16/153Legend: x=undefined, R/W=read/writeNotes:1. The contents of the I/O port DR registers are readable only in outpu

ST72334J/N, ST72314J/N, ST72124J17/1535 FLASH PROGRAM MEMORY5.1 INTRODUCTIONFLASH devices have a single voltage non-volatileFLASH memory that may be p

ST72334J/N, ST72314J/N, ST72124J18/1536 DATA EEPROM6.1 INTRODUCTIONThe Electrically Erasable Programmable ReadOnly Memory can be used as a non volatil

ST72334J/N, ST72314J/N, ST72124J19/153DATA EEPROM (Cont’d)6.3 MEMORY ACCESSThe Data EEPROM memory read/write accessmodes are controlled by the LAT bit

Table of Contents1532/15321 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 52 INTRODUCTION . . .

ST72334J/N, ST72314J/N, ST72124J20/153DATA EEPROM (Cont’d)6.4 POWER SAVING MODESWait modeThe DATA EEPROM can enter WAIT mode on ex-ecution of the WFI

ST72334J/N, ST72314J/N, ST72124J21/153DATA EEPROM (Cont’d)6.6 REGISTER DESCRIPTIONCONTROL/STATUS REGISTER (CSR)Read/WriteReset Value: 0000 0000 (00h)B

ST72334J/N, ST72314J/N, ST72124J22/1537 DATA EEPROM Register Map and Reset Values 7.1 READ-OUT PROTECTION OPTION The Data EEPROM can be optionally rea

ST72334J/N, ST72314J/N, ST72124J23/1538 CENTRAL PROCESSING UNIT8.1 INTRODUCTIONThis CPU has a full 8-bit architecture and containssix internal registe

ST72334J/N, ST72314J/N, ST72124J24/153CPU REGISTERS (Cont’d)CONDITION CODE REGISTER (CC) Read/WriteReset Value: 111x1xxxThe 8-bit Condition Code regis

ST72334J/N, ST72314J/N, ST72124J25/153CENTRAL PROCESSING UNIT (Cont’d)Stack Pointer (SP)Read/WriteReset Value: 01 FFhThe Stack Pointer is a 16-bit reg

ST72334J/N, ST72314J/N, ST72124J26/1539 SUPPLY, RESET AND CLOCK MANAGEMENTThe ST72334J/N, ST72314J/N and ST72124J mi-crocontrollers include a range of

ST72334J/N, ST72314J/N, ST72124J27/1539.1 LOW VOLTAGE DETECTOR (LVD)To allow the integration of power managementfeatures in the application, the Low V

ST72334J/N, ST72314J/N, ST72124J28/1539.2 RESET SEQUENCE MANAGER (RSM)9.2.1 IntroductionThe reset sequence manager includes three RE-SET sources as sh

ST72334J/N, ST72314J/N, ST72124J29/153RESET SEQUENCE MANAGER (Cont’d)9.2.2 Asynchronous External RESET pinThe RESET pin is both an input and an open-d

Table of Contents3/153312.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4312

ST72334J/N, ST72314J/N, ST72124J30/1539.3 MULTI-OSCILLATOR (MO)The main clock of the ST7 can be generated byfour different source types coming from th

ST72334J/N, ST72314J/N, ST72124J31/1539.4 CLOCK SECURITY SYSTEM (CSS)The Clock Security System (CSS) protects theST7 against main clock problems. To a

ST72334J/N, ST72314J/N, ST72124J32/1539.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTIONRead/WriteReset Value: 000x 000x (xxh) Bit 7:5 = Reserved, alway

ST72334J/N, ST72314J/N, ST72124J33/15310 INTERRUPTSThe ST7 core may be interrupted by one of two dif-ferent methods: maskable hardware interrupts asli

ST72334J/N, ST72314J/N, ST72124J34/153INTERRUPTS (Cont’d)Figure 18. Interrupt Processing FlowchartTable 5. Interrupt mappingNote 1. Valid for HALT and

ST72334J/N, ST72314J/N, ST72124J35/15311 POWER SAVING MODES11.1 INTRODUCTIONTo give a large measure of flexibility to the applica-tion in terms of pow

ST72334J/N, ST72314J/N, ST72124J36/153POWER SAVING MODES (Cont’d)11.3 WAIT MODEWAIT mode places the MCU in a low power con-sumption mode by stopping t

ST72334J/N, ST72314J/N, ST72124J37/153POWER SAVING MODES (Cont’d)11.4 ACTIVE-HALT AND HALT MODESACTIVE-HALT and HALT modes are the two low-est power c

ST72334J/N, ST72314J/N, ST72124J38/153POWER SAVING MODES (Cont’d)11.4.2 HALT MODEThe HALT mode is the lowest power consumptionmode of the MCU. It is e

ST72334J/N, ST72314J/N, ST72124J39/15312 I/O PORTS12.1 INTRODUCTIONThe I/O ports offer different functional modes:– transfer of data through digital i

ST72334J/N, ST72314J/N, ST72124J4/153To obtain the most recent version of this datasheet,please check at www.st.com>products>technical literatur

ST72334J/N, ST72314J/N, ST72124J40/153I/O PORTS (Cont’d)Figure 26. I/O Port General Block DiagramTable 6. I/O Port Mode OptionsLegend: NI - not imple

ST72334J/N, ST72314J/N, ST72124J41/153I/O PORTS (Cont’d)Table 7. I/O Port Configurations Notes:1. When the I/O port is in input configuration and the

ST72334J/N, ST72314J/N, ST72124J42/153I/O PORTS (Cont’d)CAUTION: The alternate function must not be ac-tivated as long as the pin is configured as inp

ST72334J/N, ST72314J/N, ST72124J43/153I/O PORTS (Cont’d)12.4 LOW POWER MODES 12.5 INTERRUPTSThe external interrupt event generates an interruptif the

ST72334J/N, ST72314J/N, ST72124J44/153I/O PORTS (Cont’d)12.5.1 Register DescriptionDATA REGISTER (DR)Port x Data RegisterPxDR with x = A, B, C, D, E o

ST72334J/N, ST72314J/N, ST72124J45/153I/O PORTS (Cont’d)Table 9. I/O Port Register Map and Reset ValuesNotes:1) The bits corresponding to unavailable

ST72334J/N, ST72314J/N, ST72124J46/15313 MISCELLANEOUS REGISTERSThe miscellaneous registers allow control overseveral different features such as the e

ST72334J/N, ST72314J/N, ST72124J47/153MISCELLANEOUS REGISTERS (Cont’d)13.3 REGISTERS DESCRIPTIONMISCELLANEOUS REGISTER 1 (MISCR1)Read/WriteReset Value

ST72334J/N, ST72314J/N, ST72124J48/153MISCELLANEOUS REGISTERS (Cont’d)MISCELLANEOUS REGISTER 2 (MISCR2)Read/WriteReset Value: 0000 0000 (00h)Bit 7:6 =

ST72334J/N, ST72314J/N, ST72124J49/15314 ON-CHIP PERIPHERALS14.1 WATCHDOG TIMER (WDG)14.1.1 IntroductionThe Watchdog timer is used to detect the occur

ST72334J/N, ST72314J/N, ST72124J5/1531 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATIONNew Features available on the ST72C334 8 or 16K FLASH/ROM with

ST72334J/N, ST72314J/N, ST72124J50/153WATCHDOG TIMER (Cont’d)The application program must write in the CR reg-ister at regular intervals during normal

ST72334J/N, ST72314J/N, ST72124J51/153WATCHDOG TIMER (Cont’d)Table 12. Watchdog Timer Register Map and Reset Values Address(Hex.)Register Label7654321

ST72334J/N, ST72314J/N, ST72124J52/15314.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)The Main Clock Controller consists of three diffe

ST72334J/N, ST72314J/N, ST72124J53/153MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)MISCELLANEOUS REGISTER 1 (MISCR1)See Section 13 on page

ST72334J/N, ST72314J/N, ST72124J54/15314.3 16-BIT TIMER14.3.1 IntroductionThe timer consists of a 16-bit free-running counterdriven by a programmable

ST72334J/N, ST72314J/N, ST72124J55/15316-BIT TIMER (Cont’d)Figure 31. Timer Block DiagramMCU-PERIPHERAL INTERFACECOUNTERALTERNATEOUTPUTCOMPAREREGISTER

ST72334J/N, ST72314J/N, ST72124J56/15316-BIT TIMER (Cont’d)16-bit Read Sequence: (from either the CounterRegister or the Alternate Counter Register).T

ST72334J/N, ST72314J/N, ST72124J57/15316-BIT TIMER (Cont’d)Figure 32. Counter Timing Diagram, internal clock divided by 2Figure 33. Counter Timing Dia

ST72334J/N, ST72314J/N, ST72124J58/15316-BIT TIMER (Cont’d)14.3.3.3 Input CaptureIn this section, the index, i, may be 1 or 2 becausethere are 2 input

ST72334J/N, ST72314J/N, ST72124J59/15316-BIT TIMER (Cont’d)Figure 35. Input Capture Block DiagramFigure 36. Input Capture Timing DiagramICIECC0CC116-B

ST72334J/N, ST72314J/N, ST72124J6/1532 INTRODUCTIONThe ST72334J/N, ST72314J/N and ST72124J de-vices are members of the ST7 microcontroller fam-ily. Th

ST72334J/N, ST72314J/N, ST72124J60/15316-BIT TIMER (Cont’d)14.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 becausethere are 2 out

ST72334J/N, ST72314J/N, ST72124J61/15316-BIT TIMER (Cont’d)Notes: 1. After a processor write cycle to the OCiHR reg-ister, the output compare function

ST72334J/N, ST72314J/N, ST72124J62/15316-BIT TIMER (Cont’d)Figure 38. Output Compare Timing Diagram, fTIMER =fCPU/2Figure 39. Output Compare Timing Di

ST72334J/N, ST72314J/N, ST72124J63/15316-BIT TIMER (Cont’d)14.3.3.5 One Pulse ModeOne Pulse mode enables the generation of apulse when an external eve

ST72334J/N, ST72314J/N, ST72124J64/15316-BIT TIMER (Cont’d)Figure 40. One Pulse Mode Timing ExampleFigure 41. Pulse Width Modulation Mode Timing Examp

ST72334J/N, ST72314J/N, ST72124J65/15316-BIT TIMER (Cont’d)14.3.3.6 Pulse Width Modulation ModePulse Width Modulation (PWM) mode enables thegeneration

ST72334J/N, ST72314J/N, ST72124J66/15316-BIT TIMER (Cont’d)14.3.4 Low Power Modes 14.3.5 Interrupts Note: The 16-bit Timer interrupt events are connec

ST72334J/N, ST72314J/N, ST72124J67/15316-BIT TIMER (Cont’d)14.3.7 Register DescriptionEach Timer is associated with three control andstatus registers,

ST72334J/N, ST72314J/N, ST72124J68/15316-BIT TIMER (Cont’d)CONTROL REGISTER 2 (CR2)Read/WriteReset Value: 0000 0000 (00h)Bit 7 = OC1E Output Compare 1

ST72334J/N, ST72314J/N, ST72124J69/15316-BIT TIMER (Cont’d)STATUS REGISTER (SR)Read OnlyReset Value: 0000 0000 (00h)The three least significant bits a

ST72334J/N, ST72314J/N, ST72124J7/1533 PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout (N versions)VDDAVSSAVDD_3VSS_3MCO / PF0BEEP / PF1PF2NCOCMP

ST72334J/N, ST72314J/N, ST72124J70/15316-BIT TIMER (Cont’d)OUTPUT COMPARE 2 HIGH REGISTER(OC2HR)Read/WriteReset Value: 1000 0000 (80h)This is an 8-bit

ST72334J/N, ST72314J/N, ST72124J71/15316-BIT TIMER (Cont’d)Table 15. 16-Bit Timer Register Map and Reset Values Address(Hex.)Register Label76543210Tim

ST72334J/N, ST72314J/N, ST72124J72/15314.4 SERIAL PERIPHERAL INTERFACE (SPI)14.4.1 Introduction The Serial Peripheral Interface (SPI) allows full-dupl

ST72334J/N, ST72314J/N, ST72124J73/153SERIAL PERIPHERAL INTERFACE (Cont’d)Figure 43. Serial Peripheral Interface Block Diagram DR Read Buffer8-Bit Shi

ST72334J/N, ST72314J/N, ST72124J74/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.4 Functional DescriptionFigure 42 shows the serial peripheral interface

ST72334J/N, ST72314J/N, ST72124J75/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.4.2 Slave ConfigurationIn slave configuration, the serial clock is rece

ST72334J/N, ST72314J/N, ST72124J76/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.4.3 Data Transfer FormatDuring an SPI transfer, data is simultaneouslyt

ST72334J/N, ST72314J/N, ST72124J77/153SERIAL PERIPHERAL INTERFACE (Cont’d)Figure 45. Data Clock Timing DiagramCPOL = 1)CPOL = 0)MISO(from master)MOSI(

ST72334J/N, ST72314J/N, ST72124J78/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.4.4 Write Collision ErrorA write collision occurs when the software tri

ST72334J/N, ST72314J/N, ST72124J79/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.4.5 Master Mode FaultMaster mode fault occurs when the master devicehas

ST72334J/N, ST72314J/N, ST72124J8/153PIN DESCRIPTION (Cont’d)Figure 3. 56-Pin SDIP Package Pinout (N versions) 525150494847464544434241161512345678910

ST72334J/N, ST72314J/N, ST72124J80/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.4.7 Single Master and Multimaster ConfigurationsThere are two types of

ST72334J/N, ST72314J/N, ST72124J81/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.5 Low Power Modes14.4.6 Interrupts Note: The SPI interrupt events are c

ST72334J/N, ST72314J/N, ST72124J82/153SERIAL PERIPHERAL INTERFACE (Cont’d)14.4.7 Register DescriptionCONTROL REGISTER (CR)Read/WriteReset Value: 0000x

ST72334J/N, ST72314J/N, ST72124J83/153SERIAL PERIPHERAL INTERFACE (Cont’d)STATUS REGISTER (SR)Read OnlyReset Value: 0000 0000 (00h)Bit 7 = SPIF Serial

ST72334J/N, ST72314J/N, ST72124J84/153SERIAL PERIPHERAL INTERFACE (Cont’d)Table 17. SPI Register Map and Reset Values Address(Hex.)Register Label76543

ST72334J/N, ST72314J/N, ST72124J85/15314.5 SERIAL COMMUNICATIONS INTERFACE (SCI)14.5.1 IntroductionThe Serial Communications Interface (SCI) offersa f

ST72334J/N, ST72314J/N, ST72124J86/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)Figure 48. SCI Block DiagramWAKEUPUNITRECEIVERCONTROLSRTRANSMITCONTROLTD

ST72334J/N, ST72314J/N, ST72124J87/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)14.5.5 Functional DescriptionThe block diagram of the Serial Control Int

ST72334J/N, ST72314J/N, ST72124J88/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)14.5.5.2 TransmitterThe transmitter can send data words of either 8 or9

ST72334J/N, ST72314J/N, ST72124J89/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)14.5.5.3 ReceiverThe SCI can receive data words of either 8 or 9bits. Wh

ST72334J/N, ST72314J/N, ST72124J9/153PIN DESCRIPTION (Cont’d)Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)MCO / PF0BEEP / PF1PF2O

ST72334J/N, ST72314J/N, ST72124J90/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)Figure 50. SCI Baud Rate and Extended Prescaler Block DiagramTRANSMITTER

ST72334J/N, ST72314J/N, ST72124J91/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)14.5.5.4 Conventional Baud Rate GenerationThe baud rate for the receiver

ST72334J/N, ST72314J/N, ST72124J92/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)14.5.6 Low Power Modes14.5.7 InterruptsThe SCI interrupt events are conn

ST72334J/N, ST72314J/N, ST72124J93/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)14.5.8 Register DescriptionSTATUS REGISTER (SR)Read OnlyReset Value: 110

ST72334J/N, ST72314J/N, ST72124J94/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)CONTROL REGISTER 1 (CR1)Read/WriteReset Value: UndefinedBit 7 = R8 Recei

ST72334J/N, ST72314J/N, ST72124J95/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)DATA REGISTER (DR)Read/WriteReset Value: UndefinedContains the Received

ST72334J/N, ST72314J/N, ST72124J96/153SERIAL COMMUNICATIONS INTERFACE (Cont’d)EXTENDED RECEIVE PRESCALER DIVISIONREGISTER (ERPR)Read/WriteReset Value:

ST72334J/N, ST72314J/N, ST72124J97/15314.6 8-BIT A/D CONVERTER (ADC)14.6.1 IntroductionThe on-chip Analog to Digital Converter (ADC) pe-ripheral is a

ST72334J/N, ST72314J/N, ST72124J98/1538-BIT A/D CONVERTER (ADC) (Cont’d)14.6.3.2 Digital A/D Conversion ResultThe conversion is monotonic, meaning tha

ST72334J/N, ST72314J/N, ST72124J99/1538-BIT A/D CONVERTER (ADC) (Cont’d)14.6.6 Register DescriptionCONTROL/STATUS REGISTER (CSR)Read/WriteReset Value: